At the present time, although microfabrication processes for semiconductor devices have been advanced, the downscaling of processes does not lead to a reduction in area of an analog circuit block as is different from a digital circuit block. Also, since a single LSI has multiple functions, power tends to be increased, so that there is a large demand for a reduction in power consumption.
Conventionally, in a multi-channel current steering DA converter, a bias circuit is often shared by a plurality of channels so as to reduce the area. Also, since the number of required channels varies depending on the operation mode, channels may be individually powered down so as to reduce the power.
An exemplary configuration of the multi-channel current steering DA converter is shown in FIG. 10. FIG. 10 illustrates a two-channel current steering DA converter.
In the multi-channel current steering DA converter (hereinafter a DA converter is abbreviated as a DAC) of FIG. 10, 1a and 1b indicate one-channel DACs, 2a and 2b indicate current source matrices, 3a and 3b indicate decoder+switch units, 4a and 4b indicate digital input signals, 5a and 5b indicate analog output terminals, 7 indicates a bias circuit, Ia and Ib indicate current sources, Iref indicates a reference current source, and I1 indicates a bias current.
The one-channel DACs 1a and 1b have current sources Ia and Ib the numbers of which depend on the number of bits, respectively. The current value of the current sources Ia and Ib is determined based on the bias current I1 and the reference current source Iref. D/A conversion is performed by the decoder+switch units 3a and 3b outputting the currents of the current sources Ia and Ib in amounts corresponding to the digital input signals 4a and 4b to the analog output terminals 5a and 5b, respectively.
The current sources Ia and Ib are arranged in matrices on a substrate. These are the current source matrices 2a and 2b. The reference current source Iref that is a current mirror source for the current sources is also provided in the current source matrix 2a so as to put the reference current source Iref in the same voltage drop and manufacture conditions as those for the current sources.
Thus, the configuration in which a reference current source is provided in a current source matrix is described in Patent Document 1.    Patent Document 1: Japanese Unexamined Patent Application Publication No. H01-277027 (FIG. 1)